This invention relates in general to a method of analyzing and monitoring discrete power supply diagnostic states, and particularly to analyzing computer microprocessor system voltages.
Linked memory random hardware failures can occur along the edges or lattices in planar memory. In planar memory structures, it is possible to have 1, 2, 4, 6, 8, 12, and 16 common lattices. For example, 4 lattices or edges occur when either 2 strips of planar memory set up back to back along with 2 other parallel strips of planar memory. The planar memory structure lattices were typically used by CISC (Complex Instruction Set Controllers).
Linked memory random hardware failures can occur when column multiplexing using one or more bits is used in dispersed physical memory. In existing dispersed memory structures, it is possible to have 1, 2, and 4 bit column multiplexing. When one bit column multiplexing is used for “n” addresses, there is the potential for 1 and 2 bit linked physical dispersed memory failures. Similar linked physical dispersed memory failures are feasible for 2 bit and 4 bit column multiplexing. Additionally 6, 8, 12, or 16 linked memory failures may occur in physically dispersed memory.